module wishbone_slave(
			 input 			  RST_I, CLK_I, STB_I, WE_I,
			 input [7:0] 	  DAT_I,
			 //output reg 	  ACK_O,
			 output 		  ACK_O,
			 output reg [7:0] DAT_O,

			 output reg [7:0] dout);

   assign ACK_O = STB_I;
   
   always@(posedge CLK_I)
	 begin
		$display("%t : RST_I=%d, STB_I=%d, WE_I=%d", $time, RST_I, STB_I, WE_I);
		
		if(!RST_I && STB_I && WE_I)
		  begin
			 dout <= DAT_I;
		  end
	 end
endmodule

module test();
   reg clk, rst;
   reg stb_o, we_o;
   reg [7:0] dat_o;
   wire 	 ack_i;
   wire [7:0] dat_i;
   
   wire [7:0] dout;
   
   wishbone_slave slave0(
						 .RST_I(rst),
						 .CLK_I(clk),
						 .STB_I(stb_o),
						 .WE_I(we_o),
						 .DAT_I(dat_o),
						 .ACK_O(ack_i),
						 .DAT_O(dat_i),
						 .dout(dout));
   
   
   initial
	 begin
		clk = 0;
		forever #5 clk = ~clk;
	 end
   
   initial
	 begin
		rst = 0; stb_o = 0; we_o = 0;
		#10 rst = 1;
		#20 rst = 0;

		#36 stb_o = 1; we_o = 1; dat_o = 8'h12;
		wait(ack_i);			//wait the ack_i turn to 1
		$display("the salve acknowledged (ack_i = 1)");
		@(posedge clk);			//wait the rising edge of clk
		#1 stb_o = 0; we_o = 0;				//transfer finished

		$finish;
	 end // initial begin
endmodule // test
